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? 2013-2014 microchip technology inc. preliminary ds40001720c-page 1 this document includes the programming specifications for the following devices: 1.0 overview the devices can be programmed using either the high-voltage in-circuit serial programming? (icsp?) method or the low-voltage icsp? method. 1.1 hardware requirements 1.1.1 high-voltage icsp programming in high-voltage icsp? mode, these devices require two programmable power supplies: one for v dd and one for the mclr /v pp pin. 1.1.2 low-voltage icsp programming in low-voltage icsp? mode, these devices can be programmed using a single v dd source in the operating range. the mclr /v pp pin does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. 1.1.2.1 single-supply icsp programming the lvp bit in configuration word 2 enables single-supply (low-voltage) icsp programming. the lvp bit defaults to a ? 1 ? (enabled) from the factory. the lvp bit may only be programmed to ? 0 ? by entering the high-voltage icsp mode, where the mclr /v pp pin is raised to v ihh . once the lvp bit is programmed to a ? 0 ?, only the high-voltage icsp mode is available and only the high-voltage icsp mode can be used to program the device. ? pic12f1612 ? PIC12LF1612 ? pic16f1613 ? pic16lf1613 ? pic16f1614 ? pic16lf1614 ? pic16f1615 ? pic16lf1615 ? pic16f1618 ? pic16lf1618 ? pic16f1619 ? pic16lf1619 note 1: the high-voltage icsp mode is always available, regardless of the state of the lvp bit, by applying v ihh to the mclr /v pp pin. 2: while in low-voltage icsp mode, mclr is always enabled, regardless of the mclre bit, and the port pin can no longer be used as a general purpose input. pic12(l)f1612/16(l)f161x memory programming specification pic12(l)f1612/16(l)f161x
pic12(l)f1612/16(l)f161x ds40001720c-page 2 preliminary ? 2013-2014 microchip technology inc. 1.2 pin utilization five pins are needed for icsp? programming. the pins are listed in tab l e 1 - 1 . table 1-1: pin descriptions during programming pin name during programming function pin type pin description icspclk icspclk i clock input ? schmitt trigger input icspdat icspdat i/o data input/output ? schmitt trigger input mclr /v pp program/verify mode p (1) program mode select/programming power supply v dd v dd p power supply v ss v ss p ground legend: i = input, o = output, p = power note 1: the programming high voltage is internally generated. to activate the program/verify mode, high voltage needs to be applied to mclr input. since the mclr is used for a level source, mclr does not draw any significant current.
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 3 pic12(l)f1612/16(l)f161x 2.0 device pinouts the pin diagrams are shown in figure 2-1 through figure 2-6 . the pins that are required for programming are listed in table 1-1 and shown in bold lettering in the pin diagrams. figure 2-1: 8-pin pd ip, soic, dfn, udfn figure 2-2: 14-pin pdip, soic, tssop figure 2-3: 16-pin qfn, uqfn 1 2 3 4 8 7 6 5 v dd ra5 ra4 mclr /v pp /ra3 v ss ra0/icspdat ra1/icspclk ra2 pic12(l)f1612 pic16(l)f1613/4/5 1 2 3 4 14 13 12 11 5 6 7 10 9 8 v dd ra5 ra4 mclr /v pp /ra3 rc5 rc4 rc3 v ss ra0/icspdat ra1/icspclk ra2 rc0 rc1 rc2 78 2 3 1 11 12 5 9 10 13 14 15 16 6 4 ra5 ra4 mclr /v pp /ra3 rc4 rc3 rc1 rc2 ra0/icspdat ra2 ra1/icspclk v ss v dd nc rc5 nc p i c 1 6(l)f1 6 1 3 rc0
pic12(l)f1612/16(l)f161x ds40001720c-page 4 preliminary ? 2013-2014 microchip technology inc. figure 2-4: 16-pin qfn figure 2-5: 20-pin pdip, soic, ssop 78 2 3 1 11 12 5 9 10 13 14 15 16 6 4 ra5 ra4 rc4 rc3 rc1 rc2 rc0 ra0/icspdat ra2 ra1/icspclk v ss v dd nc rc5 nc pic16(l)f1 6 14/ 5 mclr /v pp /ra3 pic16(l)f1618/9 1 2 3 4 20 19 18 17 5 6 7 16 15 14 v dd ra5 ra4 mclr /v pp /ra3 rc5 rc4 rc3 v ss ra0/icspdat ra1/icspclk ra2 rc0 rc1 rc2 8 9 10 13 12 11 rc6 rc7 rb7 rb4 rb5 rb6
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 5 pic12(l)f1612/16(l)f161x figure 2-6: 20-pin qfn 89 2 3 1 14 16 10 6 17 18 19 20 7 5 4 pic16(l)f1618/9 m clr /v pp /ra3 rc5 rc4 rc3 rc6 rc7 rb7 rb4 rb5 rb6 ra0/icspdat v ss v dd ra4 ra5 11 12 13 rc1 rc0 rc2 15 ra1/icspclk ra2
pic12(l)f1612/16(l)f161x ds40001720c-page 6 preliminary ? 2013-2014 microchip technology inc. 3.0 memory map the memory is broken into two sections: program memory and configuration memory. figure 3-1: pic12(l)f1612/16(l)f1613 program memory mapping 7fff h 8000 h 81ff h ffff h 2 kw implemented maps to program memory configuration memory 8000-81ffh user id location user id location user id location user id location reserved mask/rev id device id configuration word 1 configuration word 2 configuration word 3 calibration word 1 calibration word 2 calibration word 3 reserved 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h 8009h 8008h 800ah implemented 0000h maps to 0-07ffh 07ffh 800dh-81ffh 800bh 800ch
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 7 pic12(l)f1612/16(l)f161x figure 3-2: pic16(l)f1614/8 program memory mapping 7fff h 8000 h 81ff h ffff h 4 kw implemented maps to program memory configuration memory 8000-81ffh user id location user id location user id location user id location reserved mask/rev id device id configuration word 1 configuration word 2 configuration word 3 calibration word 1 calibration word 2 calibration word 3 reserved 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h 8009h 8008h 800ah implemented 0000h maps to 0-0fffh 0fffh 800dh-81ffh 800bh 800ch
pic12(l)f1612/16(l)f161x ds40001720c-page 8 preliminary ? 2013-2014 microchip technology inc. figure 3-3: pic16(l)f1615/9 program memory mapping 7fff h 8000 h 81ff h ffff h 8 kw implemented maps to program memory configuration memory 8000-81ffh user id location user id location user id location user id location reserved mask/rev id device id configuration word 1 configuration word 2 configuration word 3 calibration word 1 calibration word 2 calibration word 3 reserved 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h 8009h 8008h 800ah implemented 0000h maps to 0-1fffh 1fffh 800dh-81ffh 800bh 800ch
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 9 pic12(l)f1612/16(l)f161x 3.1 user id location a user may store identification information (user id) in four designated locations. the user id locations are mapped to 8000h-8003h. each location is 14 bits in length. code protection has no effect on these memory locations. each location may be read with code protection enabled or disabled. 3.2 revision id the revision id word is located at 8005h. this location is read-only and cannot be erased or modified. note: mplab ? ide only displays the seven least significant bits (lsb) of each user id location, the upper bits are not read. it is recommended that only the seven lsbs be used if mplab ? ide is the primary tool used to read these addresses. register 3-1: revision id: revision id register (1) rr r r r r 10 mjrrev5 mjrrev4 mjrrev3 mjrrev2 bit 13 bit 8 rrrrr r rr mjrrev1 mjrrev0 mnrev5 mnrev4 mnrev3 mnrev2 mnrev1 mnrev0 bit 7 bit 0 legend: r = readable bit p = programmable bit ?1? = bit is set ?0? = bit is cleared -n = value at por w = writable bit u = unimpl emented bit, read as ?0? x = bit is unknown bit 13 reserved: read as ? 1 ? bit 12 reserved: read as ? 0 ? bit 11-6 mjrrev<5:0>: major revision id bits bit 5-0 mnrev<5:0>: minor revision id bits note 1: this location cannot be written.
pic12(l)f1612/16(l)f161x ds40001720c-page 10 preliminary ? 2013-2014 microchip technology inc. 3.3 device id the device id word is located at 8006h. this location is read-only and cannot be erased or modified. 3.4 configuration words there are three configuration words, configuration word 1 (8007h), configuration word 2 (8008h) and configuration word 3 (8009h). the individual bits within these configurat ion words are used to enable or disable device functions such as the brown-out reset, code protection and power-up timer. register 3-2: device id: device id register (1) rrrrrr 11 dev11 dev10 dev9 dev8 bit 13 bit 8 rrrrrrrr dev7 dev6 dev5 dev4 dev3 dev2 dev1 dev0 bit 7 bit 0 legend: r = readable bit p = programmable bit ?1? = bit is set ?0? = bit is cleared -n = value at por w = writable bit u = unimplemented bit, read as ?0? x = bit is unknown bit 13 reserved: read as ? 1 ? bit 12 reserved: read as ? 1 ? bit 11-0 dev<11:0>: device id bits these bits are used to identify the part number. note 1: this location cannot be written. table 3-1: device id values device device id values dev rev pic12f1612 11 0000 0101 1000 10 xxxx xxxx xxxx PIC12LF1612 11 0000 0101 1001 10 xxxx xxxx xxxx pic16f1613 11 0000 0100 1100 10 xxxx xxxx xxxx pic16lf1613 11 0000 0100 1101 10 xxxx xxxx xxxx pic16f1614 11 0000 0111 1000 10 xxxx xxxx xxxx pic16lf1614 11 0000 0111 1010 10 xxxx xxxx xxxx pic16f1615 11 0000 0111 1100 10 xxxx xxxx xxxx pic16lf1615 11 0000 0111 1110 10 xxxx xxxx xxxx pic16f1618 11 0000 0111 1001 10 xxxx xxxx xxxx pic16lf1618 11 0000 0111 1011 10 xxxx xxxx xxxx pic16f1619 11 0000 0111 1101 10 xxxx xxxx xxxx pic16lf1619 11 0000 0111 1111 10 xxxx xxxx xxxx
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 11 pic12(l)f1612/16(l)f161x 3.5 calibration words the internal calibration values are factory calibrated and stored in calibration words 1, 2 and 3 (800ah, 800bh and 800ch). the calibration words do not participate in erase operations. the device can be erased without affecting the calibration words. register 3-3: co nfiguration word 1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 fcmen (4) ieso (4) clkouten boren1 (1) boren0 (1) ? (3) bit 13 bit 8 r/p-1 r/p-1 r/p-1 u-1 u-1 r/p-1 r/p-1 r/p-1 cp (2) mclre pwrte ? ?fosc2 (5) fosc1 fosc0 bit 7 bit 0 legend: w = writable bit ?0? = bit is cleared r = readable bit ?1? = bit is set x = bit is unknown -n = value at por u = unimplemented bit p = programmable bit bit 13 fcmen: fail-safe clock monitor enable bit (4) 1 = on - fail-safe clock monitor is enabled 0 = off - fail-safe clock monitor is disabled bit 12 ieso: internal external switchover bit (4) 1 = on - internal/external switchover (two-speed start-up) mode is enabled 0 = off - internal/external switchover mode is disabled bit 11 clkouten : clock out enable bit 1 = off - clkout function is disabled. i/o or oscillator function on clkout pin. 0 = on - clkout function is enabled on clkout pin bit 10-9 boren<1:0>: brown-out reset enable bits (1) 11 = on - brown-out reset enabled 10 = sleep - brown-out reset enabled during operation and disabled in sleep 01 = sboden - brown-out reset controlled by sboren bit of the pcon register 00 = off - brown-out reset disabled bit 8 unimplemented: read as ? 1 ? (3) bit 7 cp : code protection bit (2) 1 = off - program memory code protection is disabled 0 = on - program memory code protection is enabled bit 6 mclre: mclr /v pp pin function select bit if lvp bit = 1 (on) : this bit is ignored. if lvp bit = 0 (off) : 1 = on - mclr /v pp pin function is mclr ; weak pull-up enabled. 0 = off - mclr /v pp pin function is digital input; mclr internally disabled; weak pull-up under control of wpua register. bit 5 pwrte : power-up timer enable bit (1) 1 = off - pwrt disabled 0 = on - pwrt enabled bit 4-3 unimplemented: read as ? 1 ? note 1: enabling brown-out reset does not automatically enable power-up timer. 2: the entire program memory will be erased when the code protection is turned off. 3: this bit should be maintained as ? 1 ? when programmed. 4: these bits are only implemented on the pic16(l)f1615/9. they act as unimplemented: read as ? 1 ? on all other parts in the family. 5: this bit is forced to ? 1 ? on the pic12(l)f1612 and pic16(l)f1613/4/8.
pic12(l)f1612/16(l)f161x ds40001720c-page 12 preliminary ? 2013-2014 microchip technology inc. bit 2-0 fosc<2:0>: oscillator selection bits 111 = ech - external clock, high-power mode: on clkin pin 110 = ecm - external clock, medium-power mode: on clkin pin 101 = ecl - external clock, low-power mode: on clkin pin 100 = intosc - i/o function on osc1 pin 011 = reserved 010 = hs - hs oscillator, high-speed crystal/resona tor connected between osc1 and osc2 pins 001 = reserved 000 = reserved register 3-4: co nfiguration word 2 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 lvp (1) debug (2) lpbor borv stvren pllen bit 13 bit 8 r/p-1 u-1 u-1 u-1 u-1 r/p-1 r/p-1 r/p-1 zcd ? ? ? ?pps1way (3) wrt1 wrt0 bit 7 bit 0 legend: w = writable bit ?0? = bit is cleared r = readable bit ?1? = bit is set x = bit is unknown -n = value at por u = unimplemented bit p = programmable bit bit 13 lvp: low-voltage programming enable bit (1) 1 = on - low-voltage programming enabled 0 = off - high voltage on mclr /v pp must be used for programming bit 12 debug : debugger mode (2) 1 = off - in-circuit debugger is disabled 0 = on - in-circuit debugger is enabled bit 11 lpbor : low-power bor bit 1 = off - low-power bor is disabled 0 = on - low-power bor is enabled bit 10 borv: brown-out reset voltage selection bit 1 = low - brown-out reset voltage (v bor ) set to 1.9v on lf devic es, and 2.45v on f devices 0 = high - brown-out reset voltage (v bor ) set to 2.7v bit 9 stvren: stack overflow/underflow reset enable bit 1 = on - stack overflow or underflow will cause a reset 0 = off - stack overflow or underflow will not cause a reset bit 8 pllen: pll enable bit 1 = on - 4x pll will be enabled for external clock, if fosc = ec, or for intosc, if ircf = 8 mhz or 16 mhz 0 = off - 4x pll disabled bit 7 zcd : zcd disable bit 1 = off - zcd disabled. zcd can be enabled by setting the zcdsen bit of zcdcon 0 = on - zcd always enabled bit 6-3 unimplemented: read as ? 1 ? note 1: the lvp bit cannot be programmed to ? 0 ? when programming mode is entered via lvp. 2: the debug mode is controlled by the mplab ? ide. 3: this bit is only implemented on the pic16(l)f1614/5/8/9. it acts as unimplemented: read as ' 1 ' on all other parts in the family. register 3-3: configurat ion word 1 (continued) note 1: enabling brown-out reset does not automatically enable power-up timer. 2: the entire program memory will be erased when the code protection is turned off. 3: this bit should be maintained as ? 1 ? when programmed. 4: these bits are only implemented on the pic16(l)f1615/9. they act as unimplemented: read as ? 1 ? on all other parts in the family. 5: this bit is forced to ? 1 ? on the pic12(l)f1612 and pic16(l)f1613/4/8.
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 13 pic12(l)f1612/16(l)f161x bit 2 pps1way: ppslock bit, one-way set enable bit (3) 1 = on - the ppslock bit is permanently set after the first access sequence that sets it. 0 = off - the ppslock bit can be set and cleared as needed by the ppslock access sequence. bit 1-0 wrt<1:0>: flash memory self-write protection bits 2 kw flash memory (pic12(l)f1612/16(l)f1613) : 11 = off - write protection off 10 = boot - 000h to 1ffh write-protected, 200h to 7ffh may be modified by pmcon control 01 = half - 000h to 3ffh write-protected, 400h to 7ffh may be modified by pmcon control 00 = all - 000h to 7ffh write-protected, no addresses may be modified by pmcon control 4 kw flash memory (pic16(l)f1614/8) : 11 = off - write protection off 10 = boot - 000h to 1ffh write-protected, 200h to fffh may be modified by pmcon control 01 = half - 000h to 7ffh write-protected, 800h to fffh may be modified by pmcon control 00 = all - 000h to fffh write-protected, no addres ses may be modified by pmcon control 8 kw flash mem ory (pic16(l)f1615/9): 11 = off - write protection off 10 = boot - 0000h to 01ffh write-protected, 0200h to 1fff may be modified by pmcon control 01 = half - 0000h to 0fffh write-protected, 1000h to 1fff may be modified by pmcon control 00 = all - 0000h to 1fffh write-protected, no addres ses may be modified by pmcon control register 3-5: co nfiguration word 3 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 wdtccs2 wdtccs1 wdtccs0 wdtcws2 wdtcws1 wdtcws0 bit 13 bit 8 u-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? wdte1 wdte1 wdtcps4 wdtcps3 wdtcps2 wdtcps1 wdtcps0 bit 7 bit 0 legend: w = writable bit ?0? = bit is cleared r = readable bit ?1? = bit is set x = bit is unknown -n = value at por u = unimplemented bit p = programmable bit bit 13-11 wdtccs<2:0>: wdt input clock selector bit: 000 = wdt reference clock is the 31.0 khz lfintosc (default value) 001 = wdt reference clock is the 31.25 khz mfintosc output 010 = reserved ... 110 = reserved 111 = swc - software control, controlled by wdtcs bits bit 10-8 wdtcws<2:0>: wdt window select bits: 000 = wdtcws125 - 12.5% window open time (87.5% delay time) 001 = wdtcws25 - 25% window open time (75% delay time) 010 = wdtcws375 - 37.5% window open time (62.5% delay time) 011 = wdtcws50 - 50% window open time (50% delay time) 100 = wdtcws625 - 62.5% window open time (37.5% delay time) 101 = wdtcws75 - 75% window open time (25% delay time) 110 = wdtcws100 - 100% window open time (legacy wdt) 111 = wdtcwssw - software wdt window size control (controlled by wdtws) bit 7 unimplemented: read as ? 1 ? note 1: typical time-out based on 31 khz clock. 2: software-controlled (wdtps). register 3-4: configurat ion word 2 (continued) note 1: the lvp bit cannot be programmed to ? 0 ? when programming mode is entered via lvp. 2: the debug mode is controlled by the mplab ? ide. 3: this bit is only implemented on the pic16(l)f1614/5/8/9. it acts as unimplemented: read as ' 1 ' on all other parts in the family.
pic12(l)f1612/16(l)f161x ds40001720c-page 14 preliminary ? 2013-2014 microchip technology inc. bit 6-5 wdte<1:0>: wdt operating mode: 00 = off - wdt disabled, swdten is ignored 01 = swdten - wdt enabled/disabled by swdten bit in wdtcon0 10 = nsleep - wdt enabled while sleep = 0 , suspended when sleep = 1 ; swdten ignored 11 = on - wdt enabled regardless of sleep; swdten is ignored bit 4-0 wdtcps<4:0>: wdt period select bits: 00000 = wdtcps0 - 1:32 (1 ms period) (1) 00001 = wdtcps1 - 1:64 (2 ms period) (1) 00010 = wdtcps2 - 1:128 (4 ms period) (1) 00011 = wdtcps3 - 1:256 (8 ms period) (1) 00100 = wdtcps4 - 1:512 (16 ms period) (1) 00101 = wdtcps5 - 1:1024 (32 ms period) (1) 00110 = wdtcps6 - 1:2048 (64 ms period) (1) 00111 = wdtcps7 - 1:4096 (128 ms period) (1) 01000 = wdtcps8 - 1:8192 (256 ms period) (1) 01001 = wdtcps9 - 1:16384 (512 ms period) (1) 01010 = wdtcpsa - 1:32768 (1s period) (1) 01011 = wdtcpsb - 1:65536 (2s period) (1) 01100 = wdtcpsc - 1:131072 (4s period) (1) 01101 = wdtcpsd - 1:262144 (8s period) (1) 01110 = wdtcpse - 1:524299 (16s period) (1) 01111 = wdtcpsf - 1:1048576 (32s period) (1) 10000 = wdtcps10 - 1:2097152 (64s period) (1) 10001 = wdtcps11 - 1:4194304 (128s period) (1) 10010 = wdtcps12 - 1:8388608 (256s period) (1) 10011 = reserved ... 11110 = reserved 11111 = wdtcps1f - 1:65536 (2s period) (1), (2) register 3-5: configurat ion word 3 (continued) note 1: typical time-out based on 31 khz clock. 2: software-controlled (wdtps).
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 15 pic12(l)f1612/16(l)f161x 4.0 program/verify mode in program/verify mode, the program memory and the configuration memory can be accessed and programmed in serial fashion. icspdat and icspclk are used for the data and the clock, respectively. all commands and data words are transmitted lsb first. data changes on the rising edge of the icspclk and is latched on the falling edge. in program/verify mode both the icspdat and icspclk are schmitt trigger inputs. the sequence that enters the device into program/verify mode places all other logic into the reset state. upon entering program/verify mode, all i/os are automatically configured as high-impedance inputs and the address is cleared. 4.1 high-voltage program/verify mode entry and exit there are two different methods of entering program/verify mode via high voltage: ?v pp ? first entry mode ?v dd ? first entry mode 4.1.1 v pp ? first entry mode to enter program/verify mode via the v pp -first method the following sequence must be followed: 1. hold icspclk and icspdat low. all other pins should be unpowered. 2. raise the voltage on mclr from 0v to v ihh . 3. raise the voltage on v dd from 0v to the desired operating voltage. the v pp -first entry prevents the device from executing code pr ior to entering program/verify mode. for example, the device will execute code when configuration word 1 has mclr disabled (mclre = 0 ), the power-up timer is disabled (pwrte = 0 ), the internal oscillator is selected (f osc = 100 ), and icspclk and icspdat pins are driven by the user application. since this may prevent entry, v pp -first entry mode is strongly recommended. see the timing diagram in figure 8-2 . 4.1.2 v dd ? first entry mode to enter program/verify mode via the v dd -first method the following sequence must be followed: 1. hold icspclk and icspdat low. 2. raise the voltage on v dd from 0v to the desired operating voltage. 3. raise the voltage on mclr from v dd or below to v ihh . the v dd -first method is useful when programming the device when v dd is already applied, for it is not necessary to disconnect v dd to enter program/verify mode. see the timing diagram in figure 8-1 . 4.1.3 program/verify mode exit to exit program/verify mode take mclr to v dd or lower (v il ). see figure 8-3 and figure 8-4 . note: in systems where the v dd and mclr /v pp signals can be controlled independently, the v pp -last method of exit should be used to keep the device in reset, thereby preventing any issues that may be caused by program execution.
pic12(l)f1612/16(l)f161x ds40001720c-page 16 preliminary ? 2013-2014 microchip technology inc. 4.2 low-voltage programming (lvp) mode the low-voltage programming mode allows devices to be programmed using v dd only, without high voltage. when the lvp bit of configuration word 2 register is set to ? 1 ?, the low-voltage icsp programming entry is enabled. to disable the low-voltage icsp mode, the lvp bit must be programmed to ? 0 ?. this can only be done while in the high-voltage entry mode. entry into the low-voltage icsp program/verify modes requires the following steps: 1. mclr is brought to v il . 2. a 32-bit key sequence is presented on icspdat, while clocking icspclk. the key sequence is a specific 32-bit pattern, ' 0100 1101 0100 0011 0100 1000 0101 0000 ' (more easily remembered as mchp in ascii). the device will enter program/verify mode only if the sequence is valid. the least significant bit of the least significant nibble must be shifted in first. once the key sequence is complete, mclr must be held at v il for as long as program/verify mode is to be maintained. for low-voltage programming timing, see figure 8-8 and figure 8-9 . exiting program/verify mode is done by no longer driving mclr to v il . see figure 8-8 and figure 8-9 . note: to enter lvp mode, the lsb of the least significant nibble must be shifted in first. this differs from entering the key sequence on other parts.
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 17 pic12(l)f1612/16(l)f161x 4.3 program/verify commands the devices implement ten programming commands; each six bits in length. the commands are summarized in table 4-1 . commands that have data associated with them are specified to have a minimum delay of t dly between the command and the data. after this delay 16 clocks are required to either clock in or clock out the 14-bit data word. the first clock is for the start bit and the last clock is for the stop bit. 4.3.1 load configuration the load configuration command is used to access the configuration memory (user id locations, configuration words, calibration words). the load configuration command sets the address to 8000h and loads the data latches with one word of data (see figure 4-1 ). after issuing the load configuration command, use the in crement address command until the proper address to be programmed is reached. the address is then programmed by issuing either the begin internally timed programming or begin externally timed programming command. the only way to get back to the program memory (address 0) is to exit program/verify mode or issue the reset address command after the configuration memory has been accessed by the load configuration command. figure 4-1: load configuration table 4-1: command mapping command mapping data/note binary (msb ? lsb) hex load configuration x00000 00h 0 , data (14), 0 load data for program memory x00010 02h 0 , data (14), 0 read data from program memory x00100 04h 0 , data (14), 0 increment address x00110 06h ? reset address x10110 16h ? begin internally timed programming x01000 08h ? begin externally timed programming x11000 18h ? end externally timed programming x01010 0ah ? bulk erase program memory x01001 09h internally timed row erase program memory x10001 11h internally timed note: externally timed writes are not supported for configuration and calibration bits. any externally timed write to the configuration or calibration word will have no effect on the targeted word. x 0 0 lsb msb 0 12 3 4 5 6 1 2 15 16 icspclk icspdat 000 0 t dly
pic12(l)f1612/16(l)f161x ds40001720c-page 18 preliminary ? 2013-2014 microchip technology inc. 4.3.2 load data for program memory the load data for program memory command is used to load one 14-bit word into the data latches. the word programs into program memory af ter the begin internally timed programming or begin externally timed program ming command is issued (see figure 4-2 ). figure 4-2: load data for program memory 4.3.3 read data from program memory the read data from program memory command will transmit data bits out of the program memory map currently accessed, starting with the second rising edge of the clock input. the icspdat pin will go into output mode on the first falling clock edge, and it will revert to input mode (high-impedance) after the 16th falling edge of the clock. if the program memory is code-protected (cp ), the data will be read as zeros (see figure 4-3 ). figure 4-3: read data from program memory icspclk icspdat 1 23 45 6 1 2 15 16 x 0 0 lsb msb 0 010 0 t dly 1 2 3 4 5 6 1 2 15 16 lsb msb t dly icspclk icspdat input input output x (from programmer) x 0 001 0 icspdat (from device)
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 19 pic12(l)f1612/16(l)f161x 4.3.4 increment address the address is incremented when this command is received. it is not possible to decrement the address. to reset this counter, the user must use the reset address command or exit program/verify mode and re-enter it. if the address is incremented from address 07ffh, it will wrap-around to location 0000h. if the address is incremented from ffffh, it will wrap-around to location 8000h. figure 4-4: increment address 4.3.5 reset address the reset address command will reset the address to 0000h, regardless of the current value. the address is used in program memory or the configuration memory. figure 4-5: reset address x 0 123 4 5 6 1 2 icspclk icspdat 0 1 1 3 x x x t dly next command 0 address + 1 address x 0 12 3 4 5 6 1 2 icspclk icspdat 0 1 1 3 x x x t dly next command 1 0000h n address
pic12(l)f1612/16(l)f161x ds40001720c-page 20 preliminary ? 2013-2014 microchip technology inc. 4.3.6 begin internally timed programming a load configuration or load data for program memory command must be given before every begin programming command. programming of the addressed memory will begin after this command is received. an internal timing mechanism executes the write. the user must allow for the program cycle time, t pint , for the programming to complete. the end externally timed programming command is not needed when the begin internally timed programming is used to start the programming. the program memory address that is being programmed is not erased prior to being programmed. figure 4-6: begin inter nally timed programming 4.3.7 begin externally timed programming a load configuration or load data for program memory command must be given before every begin programming command. programming of the addressed memory will begin after this command is received. to complete the programming the end externally timed programming command must be sent in the specified time window defined by t pext (see figure 4-7 ). externally timed writes are not supported for configuration and calibration bits. any externally timed write to the configuration or calibration word will have no effect on the targeted word. figure 4-7: begin externally timed programming 12 3 4 5 6 12 icspclk icspdat 3 t pint x 1 0 0 0 x x x 0 next command x 1 0 1 23 45 61 2 icspclk icspdat 0 0 0 1 1 0 end externally timed programming command t pext 3
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 21 pic12(l)f1612/16(l)f161x 4.3.8 end externally timed programming this command is required after a begin externally timed programming command is given. this command must be sent within the time window specified by t pext after the begin externally timed programming command is sent. after sending the end externally timed programming command, an additional delay (t dis ) is required before sending the next command. this delay is longer than the delay ordinarily required between other commands (see figure 4-8 ). figure 4-8: end externally timed programming 4.3.9 bulk erase program memory the bulk erase program memory command performs two different functions dependent on the current state of the address. a bulk erase program memory command should not be issued when the address is greater than 8009h. after receiving the bulk erase program memory command the erase will not complete until the time interval, t erab , has expired. figure 4-9: bulk erase program memory address 0000h-07ffh: program memory is erased configuration words are erased address 8000h-8009h: program memory is erased configuration words are erased user id locations are erased note: the code protection configuration bit (cp ) has no effect on the bulk erase program memory command. 12 3 4 5 6 1 2 icspclk icspdat 3 t dis x 1 0 1 0 x x x 1 next command 1 23 4 5 6 12 icspclk icspdat 3 t erab x 1 1 0 0 x x x 0 next command
pic12(l)f1612/16(l)f161x ds40001720c-page 22 preliminary ? 2013-2014 microchip technology inc. 4.3.10 row erase program memory the row erase program memory command will erase an individual row. refer to tab l e 4 - 2 for row sizes of specific devices and the pc bits used to address them. if the program memory is code-protected, the row erase program memory command will be ignored. when the address is 8000h-8009h, the row erase program memory command will only erase the user id locations, regardless of the setting of the cp configuration bit. after receiving the row erase program memory command, the erase will not complete until the time interval, t erar , has expir ed. figure 4-10: row e rase program memory table 4-2: programming row size and latches devices pc row size number of latches pic12(l)f1612 <15:5> 16 16 pic16(l)f1613 <15:5> 16 16 pic16(l)f1614 <15:5> 32 32 pic16(l)f1615 <15:5> 32 32 pic16(l)f1618 <15:5> 32 32 pic16(l)f1619 <15:5> 32 32 12 3 4 5 6 12 icspclk icspdat 3 t erar x 0 1 0 0 x x x 1 next command
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 23 pic12(l)f1612/16(l)f161x 5.0 programming algorithms the devices use internal latches to temporarily store the 14-bit words used for programming. refer to table 4-2 for specific latch information. the data latches allow the user to write the program words with a single begin externally timed programming or begin internally timed programming command. the load program data or the load configuration command is used to load a single data latch. the data latch will hold the data until the begin externally timed programming or begin internally timed programming command is given. the data latches are aligned with the lsbs of the address. the pc?s address at the time the begin externally timed programming or begin internally timed programming command is given will determine which location(s) in memory are written. if more than the maximum number of data latches are written without a begin externally timed programming or begin internally timed programming command, the data in the data latches will be overwritten. the following figures show the recommended flowcharts for programming. figure 5-1: device program/verify flowchart done start bulk erase device write user ids enter programming mode write program memory (1) verify user ids write configuration words (2) verify configuration words exit programming mode verify program memory note 1: see figure 5-2 . 2: see figure 5-5 .
pic12(l)f1612/16(l)f161x ds40001720c-page 24 preliminary ? 2013-2014 microchip technology inc. figure 5-2: program memory flowchart start read data program memory data correct? report programming failure all locations done? no no increment address command from bulk erase program yes memory (1, 2) done yes note 1: this step is optional if the device has already been erased or has not been previously programmed. 2: if the device is code-protected or must be comp letely erased, then bulk erase the device per figure 5-6 . 3: see figure 5-3 or figure 5-4 . program cycle (3)
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 25 pic12(l)f1612/16(l)f161x figure 5-3: one-word program cycle begin programming wait t dis load data for program memory command (internally timed) begin programming wait t pext command (externally timed) (1) end programming wait t pint program cycle command note 1: externally timed writes are not supported for configuration and calibration bits.
pic12(l)f1612/16(l)f161x ds40001720c-page 26 preliminary ? 2013-2014 microchip technology inc. figure 5-4: multiple-word program cycle begin programming wait t pint load data for program memory command (internally timed) wait t pext end programming wait t dis load data for program memory increment address command load data for program memory begin programming command (externally timed) latch 1 latch 2 latch n increment address command program cycle command
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 27 pic12(l)f1612/16(l)f161x figure 5-5: configuration memory program flowchart start load configuration program cycle (2) read data memory command data correct? report programming failure address = 8004h? data correct? report programming failure yes no yes ye s no increment address command no increment address command done one-word one-word program cycle (2) (config. word 1) increment address command increment address command (user id) from program read data memory command from program program bulk erase memory (1) data correct? report programming failure yes no one-word program cycle (2) (config. word 2) increment address command read data memory command from program note 1: this step is optional if the device is erased or not previously programmed. 2: see figure 5-3 .
pic12(l)f1612/16(l)f161x ds40001720c-page 28 preliminary ? 2013-2014 microchip technology inc. figure 5-6: erase flowchart start load configuration done bulk erase program memory note: this sequence does not erase the calibration words.
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 29 pic12(l)f1612/16(l)f161x 6.0 code protection code protection is controlled using the cp bit in configuration word 1. when code protection is enabled, all program memory locations (0000h-07ffh) read as ? 0 ?. further programming is disabled for the program memory (0000h-07ffh). the user id locations and configuration words can be programmed and read out regardless of the code protection settings. 6.1 program memory code protection is enabled by programming the cp bit in configuration word 1 register to ? 0 ?. the only way to disable code protection is to use the bulk erase program memory command. 7.0 hex file usage in the hex file there are two bytes per program word stored in the intel ? inhx32 hex format. data is stored lsb first, msb second. because there are two bytes per word, the addresses in the hex file are 2x the address in program memory. (example: configuration word 1 is stored at 8007h. in the hex file this will be referenced as 1000eh-1000fh). 7.1 configuration word to allow portability of code, it is strongly recommended that the programmer is able to read the configuration words and user id locations from the hex file. if the configuration words information was not present in the hex file, a simple warning message may be issued. similarly, while saving a hex file, configuration words and user id information should be included. 7.2 device id if a device id is present in the hex file at 1000ch-1000dh (8006h on the part), the programmer should verify the device id against the value read from the part. on a mismatch condition the programmer should generate a warning message.
pic12(l)f1612/16(l)f161x ds40001720c-page 30 preliminary ? 2013-2014 microchip technology inc. 7.3 checksum computation the checksum is calculated by two different methods dependent on the setting of the cp configuration bit. 7.3.1 program code protection disabled with the program code protection disabled, the checksum is computed by reading the contents of the program memory locations and adding up the program memory data starting at address 0000h, up to the maximum user addressable location. any carry bit exceeding 16 bits are ignored. additionally, the relevant bits of the configuration words are added to the checksum. all unimplemented configuration bits are masked to ? 0 ?. 7.3.2 program code protection enabled when the mplab ? ide check box for dashboard ? project properties ? conf: ? building ? insert checksum in user id memory is checked, then the 16-bit checksum of the equivalent unprotected device is computed and stored in the user id. each nibble of the unprotected checksum is stored in the least significant nibble of each of the four user id locations. the most significant checksum nibble is stored in the user id at location 8000h, the second most significant nibble is stored at location 8001h, and so forth for the remaining nibbles and id locations. the protected checksums in table 7-2 assume that the insert checksum in user id memory box is checked. the checksum of a code-protected device is computed in the following manner: the least significant nibble of each user id is used to create a 16-bit value. the least significant nibble of user id location 8000h is the most significant nibble of the 16-bit value. the least significant nibble of user id location 8001h is the second most significant nibble, and so forth for the remaining user ids and 16-bit value nibbles. the resulting 16-bit value is summed with the configuration words. all unimplemented configuration bits are masked to ? 0 ?. table 7-1: configuratio n word mask values part variant config. word 1 mask config. word 2 mask config. word 3 mask pic12(l)f1612/16(l)f1613 0ee3h 3f83h 3f7fh pic16(l)f1614/8 0ee3h 3f87h 3f7fh pic16(l)f1615/9 3ee3h 3f87h 3f7fh table 7-2: checksums device config1 config2 config3 checksum unprotected protected mask word mask word mask unprotected code-protected blank 00aah first and last blank 00aah first and last pic12f1612 3fffh 3f7fh 0ee3h 3fffh 3f83h 3fffh 3f7fh 85e5h 073bh 134ah 94a0h pic16f1613 3fffh 3f7fh 0ee3h 3fffh 3f83h 3fffh 3f7fh 85e5h 073bh 134ah 94a0h pic16f1614 3fffh 3f7fh 0ee3h 3fffh 3f87h 3fffh 3f7fh 7de9h ff3fh 0b4eh 8ca4h pic16f1615 3fffh 3f7fh 3ee7h 3fffh 3f87h 3fffh 3f7fh 9dedh 1f43h 5b56h dcach pic16f1618 3fffh 3f7fh 0ee3h 3fffh 3f87h 3fffh 3f7fh 7de9h ff3fh 0b4eh 8ca4h pic16f1619 3fffh 3f7fh 3ee7h 3fffh 3f87h 3fffh 3f7fh 9dedh 1f43h 5b56h dcach PIC12LF1612 3fffh 3f7fh 0ee3h 3fffh 3f83h 3fffh 3f7fh 85e5h 073bh 134ah 94a0h pic16lf1613 3fffh 3f7fh 0ee3h 3fffh 3f83h 3fffh 3f7fh 85e5h 073bh 134ah 94a0h pic16lf1614 3fffh 3f7fh 0ee3h 3fffh 3f87h 3fffh 3f7fh 7de9h ff3fh 0b4eh 8ca4h pic16lf1615 3fffh 3f7fh 3ee7h 3fffh 3f87h 3fffh 3f7fh 9dedh 1f43h 5b56h dcach pic16lf1618 3fffh 3f7fh 0ee3h 3fffh 3f87h 3fffh 3f7fh 7de9h ff3fh 0b4eh 8ca4h pic16lf1619 3fffh 3f7fh 3ee7h 3fffh 3f87h 3fffh 3f7fh 9dedh 1f43h 5b56h dcach
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 31 pic12(l)f1612/16(l)f161x 8.0 electrical specifications refer to the device specific data sheet for absolute maximum ratings. table 8-1: ac/dc characteristics timing requirements for program/verify mode ac/dc characteristics standard operating conditions production tested at 25c sym. characteristics min. typ. max. units conditions/comments supply voltages and currents v dd v dd read/write and row erase operations v dd min. ? v dd max. v bulk erase operations 2.7 ? v dd max. v i ddi current on v dd , idle ? ? 1.0 ma i ddp current on v dd , programming ? ? 3.0 ma i pp v pp current on mclr /v pp ? ? 600 ? a v ihh high voltage on mclr /v pp for program/verify mode entry 8.0 ? 9.0 v t vhhr mclr rise time (v il to v ihh ) for program/verify mode entry ??1.0 ? s i/o pins v ih (icspclk, icspdat, mclr /v pp ) input high level 0.8 v dd ??v v il (icspclk, icspdat, mclr /v pp ) input low level ? ? 0.2 v dd v v oh icspdat output high level v dd -0.7 v dd -0.7 v dd -0.7 ??v i oh = 3.5 ma, v dd = 5v i oh = 3 ma, v dd = 3.3v i oh = 2 ma, v dd = 1.8v v ol icspdat output low level ?? v ss +0.6 v ss +0.6 v ss +0.6 v i oh = 8 ma, v dd = 5v i oh = 6 ma, v dd = 3.3v i oh = 3 ma, v dd = 1.8v programming mode entry and exit t ents programing mode entry setup time: icspclk, icspdat setup time before v dd or mclr ? 100 ? ? ns t enth programing mode entry hold time: icspclk, icspdat hold time after v dd or mclr ? 250 ? ? ? s serial program/verify t ckl clock low pulse width 100 ? ? ns t ckh clock high pulse width 100 ? ? ns t ds data in setup time before clock ? 100 ? ? ns t dh data in hold time after clock ? 100 ? ? ns t co clock ? to data out valid (during a read data command) 0 ? 80 ns t lzd clock ? to data low-impedance (during a read data command) 0 ? 80 ns t hzd clock ? to data high-impedance (during a read data command) 0 ? 80 ns t dly data input not driven to next clock input (delay required between command/data or command/ command) 1.0 ? ? ? s t erab bulk erase cycle time ? ? 5 ms t erar row erase cycle time ? ? 2.5 ms note 1: externally timed writes are not support ed for configuration and calibration bits.
pic12(l)f1612/16(l)f161x ds40001720c-page 32 preliminary ? 2013-2014 microchip technology inc. 8.1 ac timing diagrams figure 8-1: programming mode entry ? v dd first figure 8-2: programming mode entry ? v pp first t pint internally timed programming operation time ? ? ? ? 2.5 5 ms ms program memory configuration words t pext externally timed programming pulse 1.0 ? 2.1 ms note 1 t dis time delay from program to compare (hv discharge time) 300 ? ? ? s t exit time delay when exiting program/verify mode 1 ? ? ? s table 8-1: ac/dc characteristics timing requirements for program/verify mode (continued) ac/dc characteristics standard operating conditions production tested at 25c sym. characteristics min. typ. max. units conditions/comments note 1: externally timed writes are not support ed for configuration and calibration bits. v pp t enth v dd t ents icspdat icspclk v ihh v il t enth icspdat icspclk v dd t ents v pp v ihh v il
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 33 pic12(l)f1612/16(l)f161x figure 8-3: programming mode exit ? v pp last figure 8-4: programming mode exit ? v dd last t exit v pp v dd icspdat icspclk v ihh v il t exit v pp v dd icspdat icspclk v ihh v il
pic12(l)f1612/16(l)f161x ds40001720c-page 34 preliminary ? 2013-2014 microchip technology inc. figure 8-5: clock and data timing figure 8-6: write co mmand-payload timing figure 8-7: read co mmand-payload timing as icspclk t ckh t ckl t dh t ds icspdat output t co icspdat icspdat icspdat t lzd t hzd input as from input from output to input to output 12 3 4 5 6 12 15 16 x 0 lsb msb 0 t dly command next command payload icspclk icspdat x x x x x 12 3 4 5 61 2 15 16 x t dly command next command payload icspclk icspdat x x x x x (from programmer) lsb msb 0 icspdat (from device) x
? 2013-2014 microchip technology inc. preliminary ds40001720c-page 35 pic12(l)f1612/16(l)f161x figure 8-8: lvp entry (powered) figure 8-9: lvp entry (powering up) t ckl t ckh 33 clocks 0 1 2 ... 31 t dh t ds t enth lsb of pattern msb of pattern v dd mclr icspclk icspdat t ents t ckh t ckl 33 clocks note 1: sequence matching can start with no edge on mclr first. 0 1 2 ... 31 t dh t ds t enth lsb of pattern msb of pattern v dd mclr icspclk icspdat
pic12(l)f1612/16(l)f161x ds40001720c-page 36 preliminary ? 2013-2014 microchip technology inc. appendix a: revision history revision a (09/2013) initial release of this document. revision b (04/2014) added pic16(l)f1614/5/8/9 to the device family; updated figures 2-1 and 2-3; added figures 2-4 through 2-7, figure 3-2 and figure 3-3; updated registers 3-3 and 3-4; updated tables 3-1 and 4-2; added note to section 4.1.3; updated section 7.3; other minor corrections. revision c (08/2014) updated part number in figure 2-2 (14-pin pdip, soic, tssop); deleted figure 2-4 (14-pin pdip, soic, tssop); added note 3 to register 3-4; updated note 5 in register 3-3; updated tables 7-1 and 7-2; other minor corrections.
? 2013-2014 microchip technology inc. preliminary ds400001720c-page 37 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of micr ochip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2013-2014, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63276-538-3 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications c ontained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work , you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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